Multi-processing systems utilize multiple processors (e.g., central processing units (CPU)) to process data and perform desired functions. As will be appreciated, the term “processor” is used synonymously with the terms “CPU” or “core” and is readily understood by those skilled in the art. In the prior art, there exist two main types of disparate multi-processing systems: Symmetric multi-processing (SMP) and asymmetric multi-processing (ASMP).
SMP systems are typically characterized by the sharing of all system resources, a single synchronous L2 cache interface (and possibly asynchronous L2), processors are controlled at the same clock frequency and clock voltage. This also generally means the processors/cores are equally accessible to the shared memory system (such as L2 cache and memory). In SMP, clock frequencies and voltages are not individually adjustable and, therefore, cannot be changed on a per core/processor basis. In addition, the L2 cache is shared among all cores and the L2 cache frequency is not scalable on a per core basis. In most, if not all applications, workloads of the processors in SMP are unbalanced and this leads to higher power consumption. SMP may also be characterized as treating all processors/cores equally (equality).
In contrast, ASMP systems are typically characterized by having different clock frequencies and/or clock voltages individually for processors and the L2 cache clock frequency can be independently scaled. Thus, processor clock frequency and L2 cache frequency can be scaled based on workload (e.g., faster L2 cache relative to cores for memory intensive workloads). In general terms, ASMP systems are more power efficient than SMP systems, but potentially higher power consumption may be caused by the additional and more complex hardware. When the L1 cache miss rate is high, the processor will fetch data from the L2 cache. If the requested relevant data is stored in the lower clock frequency portion of the L2 cache, the processor has to wait for the data. This leads to higher latency and higher power consumption. ASMP may also be characterized as treating all processors/cores differently or unequally (inequality).
Prior U.S. patent application Ser. No. 14/580,044 (having a filing date of Dec. 22, 2014) illustrates (in its FIG. 1) and describes the basic architecture of a processing system 100 having multiple processors employing ASMP and that a similar prior art system is utilized for SMP, however, the processors operate at a single clock frequency and using a single supply voltage level—as readily understood by persons of ordinary skill in the art. Various improvements to the basic system, including (1) a hardware-based apparatus for fast and efficient dynamic switching between SMP/ASMP modes and (2) a low-cost version of an SMP/ASMP system focused on switching from one core to two cores, with the two cores operating in ASMP mode (and when more than two cores operate, operating them in SMP mode) are described therein.
Hardware-based or hardware-implemented switching, with no intervention by software, can provide faster transitioning between SMP/ASMP modes. Accordingly, there is needed a low-cost, low-power multiprocessing system or architecture that provides fast SMP/ASMP mode switching utilizing hardware-based switching methods and apparatus.